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DOE Reports Advances on Next-Gen Nanoscale Transistors, Electronics

by Editor1 last modified November 29, 2010 - 12:44

The next step in next-generation semiconductors may have been taken by researchers with the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and the University of California Berkeley.

DOE Reports Advances on Next-Gen Nanoscale Transistors, Electronics

UC Berkeley’s Ali Javey led DOE research on nanoscale transistors.

The team has reported success with a project to create a nanoscale transistor with “excellent electronic properties,” according to Ali Javey, who led the research and is a faculty scientist in Berkeley Lab’s Materials Sciences Division and a professor of electrical engineering and computer science at UC Berkeley.

Javey’s group focused on integrating ultra-thin layers of the semiconductor indium arsenide onto a silicon substrate. to create a nanoscale transistor with excellent electronic properties.

Indium arsenide several advantages over traditional silicon-based electronics, Javey said, including superior electron mobility and velocity. These properties would support future high-speed, low-power electronic devices, he added.

“We’ve shown a simple route for the heterogeneous integration of indium arsenide layers down to a thickness of 10 nanometers on silicon substrates,” Javey said. “The devices we subsequently fabricated were shown to operate near the projected performance limits of III-V devices with minimal leakage current. Our devices also exhibited superior performance in terms of current density and transconductance as compared to silicon transistors of similar dimensions.”

Javey’s research group has focused on compound III–V semiconductors, which feature superb electron transport properties. The challenge has been to find a way of plugging these compound semiconductors into today’s well-established, low-cost processing technologies.

Past efforts to show direct hetero-epitaxial growth of III-V on silicon substrates is challenging and complex, and often results in a high volume of defects.

In Detail: Compound Semiconductor-on-Insulator Technologies
Javey explained his team’s successful approach this way: “We’ve demonstrated what we are calling an ‘XOI,’ or compound semiconductor-on-insulator technology platform, that is parallel to today’s ‘SOI,’ or silicon-on-insulator platform. Using an epitaxial transfer method, we transferred ultra-thin layers of single-crystal indium- arsenide on silicon/silica substrates, and then fabricated devices using conventional processing techniques in order to characterize the XOI material and device properties,” he said.

To make their XOI platforms, Javey and his collaborators grew single-crystal indium arsenide thin films (10 to 100 nanometers thick) on a preliminary source substrate then lithographically patterned the films into ordered arrays of nanoribbons. After being removed from the source substrate through a selective wet-etching of an underlying sacrificial layer, the nanoribbon arrays were transferred to the silicon/silica substrate via a stamping process.

Javey attributed XOI transistors’ “excellent” electronic performance to the small dimensions of the active “X” layer -- and a technique called “quantum confinement,” which served to tune the material’s band structure and transport properties.

“Future research on the scalability of our process for 8-inch and 12-inch wafer processing is needed,” Javey said. “Moving forward we believe that the XOI substrates can be obtained through a wafer bonding process, but our technique should make it possible to fabricate both p- and n- type transistors on the same chip for complementary electronics based on optimal III–V semiconductors.

The results of the research appear in the journal Nature, as “Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors.”

Javey’s co-authors include: Hyunhyub Ko, Kuniharu Takei, Rehan Kapadia, Steven Chuang, Hui Fang, Paul Leu, Kartik Ganapathi, Elena Plis, Ha Sul Kim, Szu-Ying Chen, Morten Madsen, Alexandra Ford, Yu-Lun Chueh, Sanjay Krishna and Sayeef Salahuddin.

The research was funded in part by an LDRD grant from the Lawrence Berkeley National Laboratory, and by the MARCO/MSD Focus Center at MIT, the Intel Corporation and the Berkeley Sensor and Actuator Center.

Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, Calif. and conducts unclassified scientific research for DOE’s Office of Science.