Vlad P. Shmerko Ph.D.
| Position |
Department / Business Unit |
| Adjunct Professor |
Department of Electrical and Computer Engineering |
| Institution |
Disciplines |
| University of Calgary |
Engineering |
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State / Provence |
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| Country |
Website |
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link
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| Fax |
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| +1 403 2826855 |
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Dr. Shmerko's current research interests include: nanostructures, nanoarchitectronics, computer-aided design of digital circuits, and lastly, modeling and simulation in biometrics.
Education
M.Sc. in E.E., State University of Informatics & Radioelectronics, Minsk, Belarus (1976), Ph.D. in E.E., State University of Informatics & Radioelectronics, Minsk, Belarus (1984_), Dr. Habilitated in C.S./E.E., USSR (1990)
Books
(2006) S. Yanushkevich, M. Miller, V. Shmerko, R. Stankovic, Decision Diagram Techniques for Electrical Engineers (Handbook), CRC Press/Taylor&Francis (2005) S. Yanushkevich, A. Stoica, V. Shmerko, D. Popel, Inverse Problem of Biometric, CRC Press/Taylor&Francis (2006) S. Yanushkevich, V. Shmerko, Decision Diagrams Techniques, Chapter in The Electrical Engineering Handbook, CRC Press, 3rd edition (2004) S. Yanushkevich, V. Shmerko, S. Lyshevski, Logic Design of NanoICs, CRC Press
Important Articles
(2004) V. Shmerko, S. Yanushkevich, 3D Feedforward Neural Networks and its Realization by a SET Logic. In book: S. Yanushkevich (Ed.) Artificial Intelligence in Logic Design, Kluwer Academic Publishers (2004) V. Shmerko, Malyugin's Contribution to Logic Control and Logic Design, Automation and Remote Control (Kluwer/Plenum), Volume 65, Issue 6, pp. 901-918 (2004) P. Dziurzanskii, V. P. Shmerko, S. N. Yanushkevich, Representation of Logical Circuits by Linear Decision Diagrams with Extension to Nanostructures, Automation and Remote Control (Plenum/Kluwer Publishers), June 2004, Volume 65, Issue 6, p. 920-937 (2004) Shmerko V., Yanushkevich S., Dziurzanski P., Malyugin V., Tomaszewska, Linearity of Word-Level Representation of Multiple-Valued Networks, International Journal on Multiple-Valued Logic, No.6, part 2 (2003) V. Shmerko, S. Yanushkevich, Three-Dimensional Feedforward Neural Networks and Their Realization by Nano-devices, Artificial Intelligence Review Int. Journal (Kluwer Publishers), Special Issue on “Artificial Intelligence in Logic Design“, December 2003, Volume 20, Issue 3-4, pp. 473-494 (2002) Yanushkevich S., Shmerko V., Malyugin V., Dziurzanski P., Linear Models of Circuits Based on the Multivalued Components, Automation and Remote Control, vol. 63, no.6, 2002, pp. 960-980 (2002) S. Yanushkevich, P. Dziurzanski, V. Shmerko, Word-Level Models for Efficient Computation of Multiple-Valued Functions, Part 1: LAR, IEEE 32th Intl Symp. Multiple-Valued Logic, USA, pp. 202-208 (2002) A. Tomaszewska, S. Yanushkevich, V. Shmerko, Word-Level Models for Efficient Computation of Multiple-Valued Functions, Part 2: LWL, IEEE 32th Intl Symp. Multiple-Valued Logic, USA, pp. 209-214 (2001) Butler J., Dueck G., Shmerko V., Yanushkevich S., On the Number of Generators of Transeunt Triangles, Discrete Applied Mathematics (USA), no. 108, pp. 309-316 (2001) Tomaszewska A., Dziurzanski P., Yanushkevich S., Shmerko V., Two-Phase Exact Detection of Symmetries, Proc. 31-th IEEE Int. Symp., Multiple-Valued Logic, pp.213-219 (2000) Cheushev V., Yanushkevich S., Moraga C., Shmerko V., Kolodzejczyk J., Information Theory Method for Flexible Network Synthesis, Proc. IEEE 31-th Int. Symp. Multiple-Valued Logic, pp. 201-206 (2000) Butler J., Dueck G., Shmerko V., Yanushkevich S., Comments on Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expansion for Symmetric Functions, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol.19, no.11, pp. 1386-1388
Other publications: 8 books, 45 patents, over 140 journal and conference papers, 45 technical reports
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