Logic Design of NanoICS

Svetlana Yanushkevich University of Calgary
Vlad P. Shmerko University of Calgary
Sergey Edward Lyshevski Rochester Institute of Technology
Logic Design of NanoICS
Publication Type List Price
Reference $124.95 / £79.99
Publication Date Imprint
10/28/2004 CRC
Disciplines ISBN
Electronics 9780849327667
Number of Pages Buy with discount
488 buy
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Description

Today's engineers will confront the challenge of a new computing paradigm, relying on micro- and nanoscale devices. Logic Design of NanoICs builds a foundation for logic in nanodimensions and guides you in the design and analysis of nanoICs using CAD. The authors present data structures developed toward applications rather than a purely theoretical treatment.

Requiring only basic logic and circuits background, Logic Design of NanoICs draws connections between traditional approaches to design and modern design in nanodimensions. The book begins with an introduction to the directions and basic methodology of logic design at the nanoscale, then proceeds to nanotechnologies and CAD, graphical representation of switching functions and networks, word-level and linear word-level data structures, 3-D topologies based on hypercubes, multilevel circuit design, and fault-tolerant computation in hypercube-like structures. The authors propose design solutions and techniques, going beyond the underlying technology to provide more applied knowledge.

This design-oriented reference is written for engineers interested in developing the next generation of integrated circuitry, illustrating the discussion with approximately 250 figures and tables, 100 equations, 250 practical examples, and 100 problems. Each chapter concludes with a summary, references, and a suggested reading section.

Table of Contents

Preface. Acknowledgements. Introduction. Nanotechnologies. Basics of Logic Design in Nanospace. Word-level Data Structures. Nanospace and Hypercube-Like Data Structures. Nanodimensional Multilevel Circuits. Linear Word-level Models of Multilevel Circuits. Event-Driven Analysis of Hypercube-Like Topology. Nanodimensional Multivalued Circuits. Parallel Computation in Nanospace. Fault-Tolerant Computation. Information Measures in Nanodimensions. Index.

Contributors

Author 1 Yanushkevich, Svetlana N., University of Calgary, Alberta, Canada Author 2 Shmerko, Vlad P., University of Calgary, Alberta, Canada Author 3 Lyshevski, Sergey Edward, Rochester Institute of Technology, New York, USA
by siebo last modified September 14, 2009 - 13:29
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Features

  • - Builds a foundation in the design and analysis of nanoICs, the next generation of circuitry
  • - Introduces data structures that satisfy criteria of massive parallel processing, homogeneity, and fault tolerance, allowing you to choose appropriate models for a given application
  • - Discusses the models and data structures necessary for synthesis of circuits in nanodimensions
  • - Includes approximately 250 figures and tables, 100 equations, and 250 examples, illustrating the discussion and making the material more accessible
  • - Contains 100 problems plus references and suggestions for further reading, building competence in design and analysis