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The fundamental building block of modern electronic circuits is the switching element, typically a transistor, which can be used to perform computational operations when assembled into digital circuits. The number of devices on such circuits, or chips, has increased at a staggering rate, even exceeding the expectations of Moore's law, which predicts a doubling in areal density of devices about every 2 years. Devices are now routinely manufactured with submicron precision using the top-down approaches of photolithography, masking, and etching to produce complex circuits in silicon. A contemporary microprocessor produced by such methodology can have in excess of 40 million transistors, and this figure is likely to grow at least in accordance with Moore's law in the next 5 to 10 years. However, can this phenomenon continue beyond then? Beyond that horizon, the further downsizing of silicon devices throws up some seemingly insurmountable problems. The cost of manufacturing devices approaching nanoscale dimensions using top-down methodologies may well be prohibitive, but physical as well as financial constraints may prevail. Semiconductor junctions and oxide barriers may not have satisfactory performance when minimized to nanometer dimensions. For instance, ultrathin oxide barriers leak charge, or semiconductor junctions may not exhibit sufficiently developed band structure. In addition, thermal dissipation is already a problem for state-of-the-art chips and these problems will become more difficult to solve as the areal density of silicon-based devices is increased.
Given these problems on the horizon of the silicon industries road map for future miniaturization, many believe that there should be a paradigm shift in the architecture of devices. Such an approach would be the use of bottom-up methodology, in which molecular wires, nanoparticles, nanotubes, and other molecular structures are organized into functional units, using the methods of synthetic chemistry and self-assembly. Richard P. Feynman, in his classic talk, “There Is Plenty of Room at the Bottom,” envisaged the development of nanotechnologies, and these bottom-up methodologies may help us in understanding how this “room at the bottom” may be exploited. Needless to say, the wiring, addressing, and organization of large-scale arrays of nanodevices will provide immense challenges. As a result, nanotechnology is more likely to first appear in hybrid technologies that integrate elements of nanometer devices with conventional micrometer technologies. Indeed, magnetic nanoparticles are already working their way into magnetic storage technologies.